For many devices, such as field-programmable gate arrays (FPGAs) or other types of programmable logic devices (PLDs), accurate timing of input/output (I/O) interfaces is important to maintaining performance. However, as I/O interface data rates increase, the timing relationships between clock signals and data signals can become difficult to manage. For example, source-synchronized I/O interfaces may require clock or/or data signals to be delayed relative to each other for received or transmitted signals.
For received signals in particular, it can be difficult to maintain accurate timing at extremely high speeds due to the shrinking size of valid data windows and their drift caused by voltage or temperature changes. As a result, the use of fixed delay elements or fixed phase delays determined by clock cycle percentages can be insufficient to maintain accurate timing of high speed signals received by PLDs. For example, the adjustment of programmed delay amounts by low speed PLD logic can incur data loss when delay amounts are changed while high speed received data signals are transitioning between data values. In addition, duty cycle distortion can become a significantly larger portion of valid data windows as the size of the valid data windows shrink.
Also, for high speed serial communications, it is often preferable for data and clock signals to be recovered from a single high speed serial link within short lock times, such as on the order of tens of bits. This can be problematic for existing I/O interfaces designed to perform clock data recovery over longer lock times of hundreds or even one thousand bits.
Another approach to recovering data and clock signals from serial links to PLDs involves dedicated hardware to capture data using multiple clock phases (for example, 8 phases). However, such implementations are complicated by the chip area consumed by such dedicated hardware and the resynchronization of captured data into a common clock domain.
Accordingly, there is a need for an improved approach to reducing these various problems associated with the timing of high speed signals. In particular, there is a need to facilitate accurate timing of signals linked to PLDs and other device types.